Modern electronics rely heavily on memory because memory is central to a vast majority of computing operations. For example, running an application on a device, such as a cell phone, a table, personal computer or other device, will require the utilization of memory. This memory can be in the form of persistent storage such as solid state drives (SSDs), hard disk drives (HDDs) or even tape drives. However, persistent storage tends to be slower than non-persistent storage such as random access memory (RAM).
The high bandwidth memory dynamic random access memory (HBM DRAM) specification lists two modes of operation: legacy mode and pseudo channel mode. The two modes of operation depend on channel density and are fixed by the design of the memory array. In a conventional HBM DRAM system, a device can support either legacy mode or pseudo channel mode, but not both.
In legacy mode, each read or write transaction transfers 256 bit pre-fetch memory (2×128) bit in a burst that consists of 2 cycles of 128 bits each. In pseudo channel mode, the 128-bit bus is split into 2 individual 64-bit segments. On each segment, a read or write transaction transfers 256 bits as well, but in a burst that lastas 4 cycles (of 64 bits each).
The pseudo channel concept essentially divides the memory of a single channel in half and assigns each half to a fixed pseudo channel. Each read access or write access is internally executed as two seamless array accesses. Both pseudo channels operate semi-independent because they share the same address and command bus (e.g., you can send a command and address to one pseudo channel or the other, but not both) and the same CK and CKE inputs, but decode and execute commands individually. The pre-fetch as seen by the memory controller is therefore 256 bit per pseudo channel (2×128 bit).
The pseudo channel mode HBM has two independent sub channels, each having half the port data width size compared to the port data width of legacy mode. The two sub channel share a command pin and shares a low power/mode register setting, but have separated data pins. Most common conventional HBM controllers contain two read/write traffic channels to support pseudo channel mode. Therefore, each separate channel has the same command path and half width port data path as legacy mode to handle the traffic of each pseudo channel.
The conventional pseudo channel mode architecture has several shortcomings. First, the conventional pseudo channel mode architecture only supports pseudo channel mode and is not compatible to legacy mode because legacy mode only needs one command channel and 32 bytes port data width. Second, the two pseudo channel sub controllers cannot keep synchronous over a long period of time because the two ports are handled by different hosts which act independent of each other. To achieve the optimal system performance, the two ports should be accessed synchronously or with the same access length.
Furthermore, in conventional pseudo channel modes, the duplicated traffic channels contribute to more area, digital circuit control logic and power consumption. A drawback to the conventional pseudo-channel method is that while the port data path of each pseudo channel is half of that in legacy mode, the total data path costs the same hardware recourse as in legacy mode. Each pseudo channel needs an independent command control logic so the command path must be duplicated. This causes each pseudo channel to have separate port command buffers, command queue, and DDR PHY convertors.
As described above, pseudo channel mode needs to support two channels (e.g., two host ports), but legacy mode only needs one channel controller (e.g., one host port). Therefore, in conventional systems, HBM controllers must have two separate implementation architectures to support both legacy mode and pseudo channel mode separately. This method implements a single architecture to support both pseudo channel mode and legacy mode by using a single command channel to support pseudo channel mode will save die size and power consumption.
Therefore, there is a need for to use a single command channel and single data channel to support both pseudo channel mode and legacy mode in a single architecture.